Cadence Virtuoso 8-bit adder design

Design a 8-bit carry-ripple adder and optimize your design for delay. Report the layout and schematic picture, LVS outcome and post-layout extracted simulation waveforms for at least 4input combinations. Use simulation parameters similar to the ones used for the previous lab assignments. Report the worst case delay in your circuit.

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Cadence Virtuoso 8-bit adder design

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